1. Field of the Invention
The present invention relates to a low power-supply voltage detection circuit, and more particularly to a low power-supply voltage detection circuit for detecting low power-supply voltage when a drop occurs in the power-supply voltage that is supplied to a nonvolatile memory.
2. Description of the Related Art
In the prior art, an internal high voltage is generated from the power-supply voltage by means of a booster circuit in order to write data or erase a page in nonvolatile memory.
The current-voltage characteristic of the internal high voltage generated from the booster circuit is dependent on the power-supply voltage, the internal high voltage typically increasing and the current supply capability improving with increase in the power-supply voltage. Conversely, decrease in the power-supply voltage results in lower internal high voltage and poor current supply capability.
When writing data and erasing pages at a power-supply voltage that is lower than operation specifications, the internal high voltage often fails to attain an adequate current-voltage characteristic, whereby incorrect data are written or data are corrupted. At a low power-supply voltage that does not ensure data writing or page erasing, control is effected such that data writing or page erasing in a nonvolatile memory is suspended.
FIG. 1 is a circuit diagram of a low power-supply voltage detection circuit disclosed in Japanese Patent Laid-open No. 8599/1989 that detects low power-supply voltage in order to exercise this type of control. This low power-supply voltage detection circuit comprises: resistor 901 and zener diode 902 connected together in series between power-supply voltage Vcc and ground; resistors 903 and 904 that are connected together in series between ground and the connection point of resistor 901 and zener diode 902; resistors 905 and 906 that are connected together in series between power-supply voltage Vcc and ground; comparator 907; and booster circuit 908.
The fixed voltage that is taken from the connection point of resistor 901 and zener diode 902 is voltage-divided at resistors 903 and 904 and supplied as a reference voltage to one of the input terminals of comparator 907. On the other hand, voltage obtained by voltage-dividing the power-supply voltage from the connection point of resistors 905 and 906 is led out and supplied to the other input terminal of comparator 907. Comparator 907 compares this voltage-divided voltage with the reference voltage, outputs high level to booster circuit 908 when the voltage-divided voltage is higher than the reference voltage, and outputs low level to booster circuit 908 when the voltage-divided voltage is equal to or lower than the reference voltage.
Power is thus not supplied to booster circuit 908 if the power-supply voltage is equal to or lower than a prescribed value, and operations such as data writing to the nonvolatile memory are halted.
However, even in cases in which the nonvolatile memory is operating at an adequate power-supply voltage, there are cases in which power-supply voltage undershoot occurs in which the power-supply voltage drops for an extremely short interval. In this case, the low power-supply voltage detection circuit detects the low power-supply voltage regardless of whether the operation of the nonvolatile memory is affected or not, and operations such as data writing are subjected to unpredictable halts. As shown in FIG. 2, with each occurrence of undershoot of the power-supply voltage, the output of comparator 907 switches to low level and operations such as data writing to a nonvolatile memory are halted. This phenomenon tends to occur when the operating power-supply voltage of the nonvolatile memory is low, or in a state in which a read operation is carried out in parallel with a write operation or an erase operation, such as when performing parallel operations such as a dual read. The same also holds true for a case of operating a charging-pump booster circuit at a low power-supply voltage and supplying a high current such as in CHE (Channel Hot Electron) mode flash memory.
It is an object of the present invention to provide a low power-supply voltage detection circuit that is capable of detecting low power-supply voltage without suspending such operations as data writing during instances of power-supply voltage undershoot of extremely short duration.
The low power-supply voltage detection circuit of the present invention detects drops in the power-supply voltage that is supplied to a nonvolatile memory that is capable of performing data writing and/or page erasing when a memory control signal is active, and comprises: a reference voltage generation means; a power supply voltage dividing means; a comparison means; and a low power-supply voltage control means.
The reference voltage generation means generates and outputs a fixed voltage as a reference voltage. The power supply voltage dividing means divides a voltage between the power-supply voltage and ground voltage and outputs this voltage as a voltage-divided voltage. The comparison means compares the reference voltage and voltage-divided voltage, turns the low power-supply voltage signal OFF when the voltage-divided voltage is higher than the reference voltage, and turns the low power-supply voltage signal ON and outputs the signal when the voltage-divided voltage is lower than the reference voltage. The low power-supply voltage control means effects control such that a memory control signal switching operation is either halted or enabled for a prescribed time interval; the memory control signal switching operation being an operation in which a memory control signal is activated and output when this low power-supply voltage signal is OFF and switched from active to inactive when the low power-supply voltage signal changes from the OFF state to the ON state.
The nonvolatile memory should be capable of performing at least one of data writing and page erasing, and be capable of switching between activity and inactivity of these operations by means of an input signal. A general-purpose flash memory can therefore be employed.
The reference voltage generation means can be constituted by generally used circuits such as a combination of zener diodes and resistors. A variety of circuits, such as an amplification circuit for amplification and output, can be used according to the specifications of the nonvolatile memory.
The power supply voltage-dividing means may be constituted by a generally known circuit. For example, a plurality of resistors may be connected together in series between the power supply line and ground and voltage then extracted from connection points between the resistors.
When voltage-dividing the power-supply voltage, the value of the voltage-divided voltage may be adjusted such that the ratio of the reference voltage to the voltage for performing the memory control signal switching operation is the same as the ratio of the voltage-divided voltage to the power-supply voltage. Of course, the value of the reference voltage may also be varied and adjusted.
The comparison means should have the functions of receiving and comparing the above-described reference voltage and voltage-divided voltage and switching the level of the output signal according to the size of the voltage-divided voltage with respect to the reference voltage, and a general-purpose comparator may therefore be used. The output signal is applied to the low power-supply voltage control means as the low power-supply voltage signal. Here, a circuit for dealing with hazards for preventing erroneous operation halts may be added to the low power-supply voltage signal output.
Since the ratio of the reference voltage to the voltage for performing the memory control signal switching operation is the same as the ratio of the voltage-divided voltage to the power-supply voltage, the level of the low power-supply voltage signal is switched according to the size of the actual power-supply voltage to the voltage for performing the memory control signal switching operation.
The low power-supply voltage control means activates the memory control signal when this low power-supply voltage signal is ON and outputs the signal to the nonvolatile memory. The memory control signal switching operation, in which the memory control signal is switched from active to inactive when the low power-supply voltage signal changes from OFF to ON, is then halted or performed for a prescribed time interval.
The voltage-divided voltage becomes higher than the reference voltage when the power-supply voltage is higher than the voltage for performing the memory control signal switching operation. Upon receipt of a voltage-divided voltage and reference voltage to the comparison means, the comparison means places the low power-supply voltage signal in the OFF state. The low power-supply voltage control means then receives the low power-supply voltage signal, which is OFF. When the low power-supply voltage signal is OFF, the low power-supply voltage control means activates the memory control signal. This memory control signal is applied to the nonvolatile memory, whereby the nonvolatile memory can perform data writing and page erasing.
The voltage-divided voltage becomes lower than the reference voltage when the power-supply voltage is lower than the voltage for performing the memory control signal switching operation. The comparison means then turns ON the low power-supply voltage signal, whereby the low power-supply voltage control means receives a low power-supply voltage signal that is ON. At this time, the low power-supply voltage control means either halts or allows execution for a prescribed time period of the memory control signal switching operation in which the memory control signal is switched from active to inactive. In this way, the memory control signal is switched between active and inactive when the low power-supply voltage signal is ON, whereby data writing and page erasing of the nonvolatile memory is halted or executed as necessary.
Voltage drops of extremely short duration tend to occur upon the start of operation of internal circuits that act as a source of power supply noise such as an internal high-voltage booster circuit, an output buffer, or a sense amplifier. Such power-supply voltage undershoots of extremely short duration do not substantially affect the operation of the nonvolatile memory. Thus, in the first embodiment of the present invention, the low power-supply voltage control means halts the memory control signal switching operation for a prescribed time interval from the start of operation of an internal circuit of a semiconductor device.
In other words, the operating efficiency of the nonvolatile memory can be raised because low power-supply voltage that is caused by noise originating in internal circuits of the semiconductor device is not detected, i.e., operations such as data writing are not halted in time intervals in which power-supply voltage undershoots are predicted. Voltage drops of extremely short duration also tend to occur upon the start of an internal operation sequence in data writing or page erasing of a nonvolatile memory. According to another embodiment of the present invention, when the nonvolatile memory is in the midst of data writing or page erasing, the low power-supply voltage control means suspends the memory control signal switching operation for a prescribed time interval from the time of starting these internal operation sequences.
In other words, low power-supply voltage caused by power-supply voltage undershoots of extremely short duration at the time of starting an internal operation sequence which have no substantial effect upon the operation of the nonvolatile memory are not detected, and operations such as data writing are not halted, thereby enabling an improvement in the operating efficiency of the nonvolatile memory.
The interval of a power-supply voltage undershoot of extremely short duration is shorter than the data reading cycle of the nonvolatile memory. In another embodiment of the present invention, the time interval from halting the memory control signal switching operation until the return to an executable state is less than the read cycle of a read operation that is performed as a parallel operation with data writing or page erasing of the nonvolatile memory.
In other words, the time interval in which operations such as data writing are not halted at the time of low power-supply voltage is made shorter than the data read cycle of the nonvolatile memory. As a result, low power-supply voltage can be detected while easily distinguishing between a power-supply voltage undershoot of extremely short duration and a drop in the power-supply voltage that would essentially necessitate halting operations such as data writing.
In this case, halting of operations such as data writing may be limited to sequences that require halting of operations such as data writing in an internal operation sequence in which the nonvolatile memory is in the midst of data writing or page erasing. In another embodiment of the present invention, a low power-supply voltage control means executes the memory control signal switching operation only during the period of a prescribed internal operation sequence when the nonvolatile memory is in the process of data writing or page erasing.
In other words, low power-supply voltage detection is carried out such that operations such as data writing are not halted despite the occurrence of a power-supply voltage undershoot of extremely short duration in a sequence that does not require halting of an operation such as data writing, thereby enabling an increase in operating efficiency of the nonvolatile memory.
The intervals that require a halt of data writing are the writing verify sequence interval and writing sequence interval. In another embodiment of the present invention, when the nonvolatile memory is in the midst of data writing, a low power-supply voltage control means executes memory control signal switching operation only for a writing verify sequence interval and writing sequence interval.
In other words, a signal indicating low power-supply voltage is not output for sequences other than a writing verify sequence interval and writing sequence interval during data writing despite the occurrence of a power-supply voltage undershoot of extremely short duration. In this way, an improvement can be obtained in the operating efficiency of the nonvolatile memory.
The intervals that require a halt of page erasing are the erase verify sequence interval and the erase sequence interval. In another embodiment of the present invention, when the nonvolatile memory is in the midst of page erasing, the low power-supply voltage control means executes the above-described memory control signal switching operation only in an erase verify sequence interval and erase sequence interval.
In other words, a signal indicating a low power-supply voltage is not output despite the occurrence of a power-supply voltage undershoot of extremely short duration for cases other than for an erase verify sequence interval and erase sequence interval during page erasing. In this way, an improvement can be obtained in the operating efficiency of the nonvolatile memory. In this case, the voltage at which operations such as data writing are halted may be switched according to the internal operating sequence of the nonvolatile memory. Thus, in another embodiment of the present invention, a power supply voltage dividing means includes a means for outputting a plurality of voltage-divided voltages and a means for switching these voltage-divided voltages according to the internal operating sequence when the nonvolatile memory is in the process of writing data or erasing pages.
In other words, since a low power-supply voltage is detected while switching between a plurality of voltage-divided voltages, the optimum voltage for halting operations such as data writing can be set according to the internal operating sequence of the nonvolatile memory. Halting of operations such as data writing is therefore not performed any more than necessary, and in this way, an improvement can be obtained in the operating efficiency of the nonvolatile memory.
Furthermore, approaches other than providing a plurality of voltage-divided voltages may be adopted for switching the voltage for halting operations such as data writing. In another embodiment of the present invention, the reference voltage generation means includes a means for outputting a plurality of reference voltages and a means for switching these reference voltages according to the internal operating sequence when the nonvolatile memory is in the process of data writing or page erasing. In other words, low power-supply voltage is detected while switching between a plurality of reference voltages, thereby enabling setting of the optimum voltage for halting operations such as data writing according to internal operating sequence. Halting of operations such as data writing is therefore not performed more than necessary, and the operating efficiency of the nonvolatile memory is correspondingly improved.
The above and other objects, features, and advantages of the present invention will become apparent from the following description based on the accompanying drawings which illustrate examples of preferred embodiments of the present invention.